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authorClifford Wolf <clifford@clifford.at>2013-06-15 13:50:38 +0200
committerClifford Wolf <clifford@clifford.at>2013-06-15 13:50:38 +0200
commitc09b66b2a1002c66686e89e829aae852c9774593 (patch)
tree004e60b4fdc6bc4a5a256902d3fa039d092f4ad4 /passes
parent6ef8c6fb8a33f677580c26c2f1129d509ceec768 (diff)
Added support for "assign" statements in abc vlparse
Diffstat (limited to 'passes')
-rw-r--r--passes/abc/abc.cc8
-rw-r--r--passes/abc/vlparse.cc33
2 files changed, 39 insertions, 2 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 5ceaeb48..94adf6d0 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -572,6 +572,14 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
}
}
+ for (auto conn : mapped_mod->connections) {
+ if (!conn.first.is_fully_const())
+ conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.chunks[0].wire->name)]);
+ if (!conn.second.is_fully_const())
+ conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.chunks[0].wire->name)]);
+ module->connections.push_back(conn);
+ }
+
for (auto &it : cell_stats)
log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
int in_wires = 0, out_wires = 0;
diff --git a/passes/abc/vlparse.cc b/passes/abc/vlparse.cc
index 5c0cb7e2..fe10f57b 100644
--- a/passes/abc/vlparse.cc
+++ b/passes/abc/vlparse.cc
@@ -53,12 +53,12 @@ static int lex(FILE *f)
return token(lex_tok);
if (('a' <= ch && ch <= 'z') || ('A' <= ch && ch <= 'Z') ||
- ('0' <= ch && ch <= '9') || ch == '_') {
+ ('0' <= ch && ch <= '9') || ch == '_' || ch == '\'') {
lex_str = char(ch);
while (1) {
ch = getc(f);
if (('a' <= ch && ch <= 'z') || ('A' <= ch && ch <= 'Z') ||
- ('0' <= ch && ch <= '9') || ch == '_') {
+ ('0' <= ch && ch <= '9') || ch == '_' || ch == '\'') {
lex_str += char(ch);
continue;
}
@@ -143,6 +143,35 @@ RTLIL::Design *abc_parse_verilog(FILE *f)
}
}
}
+ else if (lex_str == "assign")
+ {
+ std::string lhs, rhs;
+
+ if (lex(f) != 256)
+ goto error;
+ lhs = lex_str;
+
+ if (lex(f) != '=')
+ goto error;
+ if (lex(f) != 256)
+ goto error;
+ rhs = lex_str;
+
+ if (lex(f) != ';')
+ goto error;
+
+ if (module->wires.count(RTLIL::escape_id(lhs)) == 0)
+ goto error;
+
+ if (rhs == "1'b0")
+ module->connections.push_back(RTLIL::SigSig(module->wires.at(RTLIL::escape_id(lhs)), RTLIL::SigSpec(0, 1)));
+ else if (rhs == "1'b1")
+ module->connections.push_back(RTLIL::SigSig(module->wires.at(RTLIL::escape_id(lhs)), RTLIL::SigSpec(1, 1)));
+ else if (module->wires.count(RTLIL::escape_id(rhs)) > 0)
+ module->connections.push_back(RTLIL::SigSig(module->wires.at(RTLIL::escape_id(lhs)), module->wires.at(RTLIL::escape_id(rhs))));
+ else
+ goto error;
+ }
else
{
std::string cell_type = lex_str;