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authorClifford Wolf <clifford@clifford.at>2014-01-03 18:17:28 +0100
committerClifford Wolf <clifford@clifford.at>2014-01-03 18:17:28 +0100
commitc44e1bec6d2a549abb9d56c98e41c23bc698e12d (patch)
tree141df05188ae4235c7ded4c5fc70d771da1377ac /passes
parent8f11eaaca6259e817df47d47df4acd8e77948d7f (diff)
More freduce cleanups
Diffstat (limited to 'passes')
-rw-r--r--passes/sat/freduce.cc24
1 files changed, 24 insertions, 0 deletions
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index 23ab8a04..44c095d2 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -52,6 +52,22 @@ struct equiv_bit_t
}
};
+struct CountBitUsage
+{
+ SigMap &sigmap;
+ std::map<RTLIL::SigBit, int> &cache;
+
+ CountBitUsage(SigMap &sigmap, std::map<RTLIL::SigBit, int> &cache) : sigmap(sigmap), cache(cache) { }
+
+ void operator()(RTLIL::SigSpec &sig)
+ {
+ std::vector<RTLIL::SigBit> vec = sigmap(sig).to_sigbit_vector();
+ for (auto &bit : vec) {
+ log("%s %d\n", log_signal(bit), cache[bit]++);
+ }
+ }
+};
+
struct FindReducedInputs
{
SigMap &sigmap;
@@ -478,6 +494,9 @@ struct FreduceWorker
worker.analyze(equiv);
}
+ std::map<RTLIL::SigBit, int> bitusage;
+ module->rewrite_sigspecs(CountBitUsage(sigmap, bitusage));
+
log(" Rewiring %d equivialent groups:\n", int(equiv.size()));
int rewired_sigbits = 0;
for (auto &grp : equiv)
@@ -492,6 +511,11 @@ struct FreduceWorker
continue;
}
+ if (grp[i].bit.wire->port_id == 0 && bitusage[grp[i].bit] <= 1) {
+ log(" Skipping unused slave: %s\n", log_signal(grp[i].bit));
+ continue;
+ }
+
log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit));
RTLIL::Cell *drv = drivers.at(grp[i].bit).first;