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authorClifford Wolf <clifford@clifford.at>2014-08-15 02:40:46 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-15 02:40:46 +0200
commitca8711644975c128d45fd8e9434439c1266c00ac (patch)
treed142e82fe2dbdebf77635a05862b383c81167e3b /passes
parent8ff71b5ae506306d7981eb118874cd4f407b2bf8 (diff)
More idstring sort_by_* helpers and fixed tpl ordering in techmap
Diffstat (limited to 'passes')
-rw-r--r--passes/fsm/fsm_expand.cc8
-rw-r--r--passes/opt/opt_clean.cc4
-rw-r--r--passes/techmap/techmap.cc6
3 files changed, 9 insertions, 9 deletions
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index 77821326..d1364391 100644
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -30,12 +30,12 @@ struct FsmExpand
RTLIL::Module *module;
RTLIL::Cell *fsm_cell;
SigMap assign_map;
- SigSet<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> sig2driver, sig2user;
+ SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> sig2driver, sig2user;
CellTypes ct;
- std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> merged_set;
- std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> current_set;
- std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> no_candidate_set;
+ std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> merged_set;
+ std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> current_set;
+ std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> no_candidate_set;
bool already_optimized;
int limit_transitions;
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index c620531e..d47e4513 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -34,7 +34,7 @@ static int count_rm_cells, count_rm_wires;
static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
{
SigMap assign_map(module);
- std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> queue, unused;
+ std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> queue, unused;
SigSet<RTLIL::Cell*> wire2driver;
for (auto &it : module->cells_) {
@@ -65,7 +65,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
while (queue.size() > 0)
{
- std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> new_queue;
+ std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> new_queue;
for (auto cell : queue)
unused.erase(cell);
for (auto cell : queue) {
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index a7f91e86..59173393 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -251,7 +251,7 @@ struct TechmapWorker
}
bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
- const std::map<RTLIL::IdString, std::set<RTLIL::IdString>> &celltypeMap, bool in_recursion)
+ const std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> &celltypeMap, bool in_recursion)
{
std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
@@ -898,7 +898,7 @@ struct TechmapPass : public Pass {
}
map->modules_.swap(modules_new);
- std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
+ std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
for (auto &it : map->modules_) {
if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) {
char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str());
@@ -960,7 +960,7 @@ struct FlattenPass : public Pass {
TechmapWorker worker;
worker.flatten_mode = true;
- std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
+ std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
for (auto &it : design->modules_)
celltypeMap[it.first].insert(it.first);