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authorClifford Wolf <clifford@clifford.at>2013-11-07 11:54:59 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-07 11:54:59 +0100
commitdb42a8f89b283d9e43d288f2dc547f2e1037f595 (patch)
tree3b5128f3d477ed6347582698fe7ed2a6287fda60 /passes
parent536621a98ba6fd41bf170f5ad469df17f73ed2c8 (diff)
Fixed $eq/$ne bitwise optimization in opt_const
Diffstat (limited to 'passes')
-rw-r--r--passes/opt/opt_const.cc15
1 files changed, 8 insertions, 7 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 34d0f924..b04ed9e7 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -146,16 +146,15 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (cell->type == "$eq" || cell->type == "$ne")
{
+ RTLIL::SigSpec a = cell->connections["\\A"];
+ RTLIL::SigSpec b = cell->connections["\\B"];
+
if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) {
int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
- cell->connections["\\A"].extend(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
- cell->connections["\\B"].extend(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
- cell->parameters["\\A_WIDTH"] = width;
- cell->parameters["\\B_WIDTH"] = width;
+ a.extend(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
+ b.extend(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
}
- RTLIL::SigSpec a = cell->connections["\\A"];
- RTLIL::SigSpec b = cell->connections["\\B"];
RTLIL::SigSpec new_a, new_b;
a.expand(), b.expand();
@@ -179,7 +178,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
if (new_a.width == 0) {
- replace_cell(module, cell, "empty", "\\Y", RTLIL::SigSpec(cell->type == "$eq" ? RTLIL::State::S1 : RTLIL::State::S0));
+ RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type == "$eq" ? RTLIL::State::S1 : RTLIL::State::S0);
+ new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
+ replace_cell(module, cell, "empty", "\\Y", new_y);
goto next_cell;
}
}