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authorClifford Wolf <clifford@clifford.at>2014-03-07 18:44:23 +0100
committerClifford Wolf <clifford@clifford.at>2014-03-07 18:44:23 +0100
commite3b11ea2d64724102070f96e667c4dea07c0c3e5 (patch)
treeed0ec44fb854d3b21564678da72de6cdc414e3f1 /passes
parent6f8865d81ab6392bdd1413f0ae6f5a5774524d28 (diff)
Fixed bug in freduce command
Diffstat (limited to 'passes')
-rw-r--r--passes/sat/freduce.cc30
1 files changed, 30 insertions, 0 deletions
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index eb94cad2..d4b7b5c1 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -560,6 +560,31 @@ struct FreduceWorker
{
}
+ bool find_bit_in_cone(std::set<RTLIL::Cell*> &celldone, RTLIL::SigBit needle, RTLIL::SigBit haystack)
+ {
+ if (needle == haystack)
+ return true;
+ if (haystack.wire == NULL || needle.wire == NULL || drivers.count(haystack) == 0)
+ return false;
+
+ std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> &drv = drivers.at(haystack);
+
+ if (celldone.count(drv.first))
+ return false;
+ celldone.insert(drv.first);
+
+ for (auto &bit : drv.second)
+ if (find_bit_in_cone(celldone, needle, bit))
+ return true;
+ return false;
+ }
+
+ bool find_bit_in_cone(RTLIL::SigBit needle, RTLIL::SigBit haystack)
+ {
+ std::set<RTLIL::Cell*> celldone;
+ return find_bit_in_cone(celldone, needle, haystack);
+ }
+
void dump()
{
std::string filename = stringf("%s_%s_%05d.il", dump_prefix.c_str(), RTLIL::id2cstr(module->name), reduce_counter);
@@ -674,6 +699,11 @@ struct FreduceWorker
continue;
}
+ if (find_bit_in_cone(grp[i].bit, grp.front().bit)) {
+ log(" Skipping dependency of master: %s\n", log_signal(grp[i].bit));
+ continue;
+ }
+
log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit));
RTLIL::Cell *drv = drivers.at(grp[i].bit).first;