diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-10-24 11:37:54 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-24 11:37:54 +0200 |
| commit | e679a5d04633e0c0626057ed2760ddb9595eea5d (patch) | |
| tree | cce75cbef78ff294cc26a992347fe16b713db996 /passes | |
| parent | e9dede01ca8834ea3c211862a5d6c0119b2b578a (diff) | |
Fixed handling of boolean attributes (passes)
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/show.cc | 4 | ||||
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 4 | ||||
| -rw-r--r-- | passes/opt/opt_clean.cc | 2 | ||||
| -rw-r--r-- | passes/proc/proc_mux.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/iopadmap.cc | 2 |
5 files changed, 7 insertions, 7 deletions
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 07e97e0f..0721d4fd 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -477,7 +477,7 @@ struct ShowWorker if (!design->selected_module(module->name)) continue; if (design->selected_whole_module(module->name)) { - if (module->attributes.count("\\placeholder") > 0) { + if (module->get_bool_attribute("\\placeholder") > 0) { log("Skipping placeholder module %s.\n", id2cstr(module->name)); continue; } else @@ -617,7 +617,7 @@ struct ShowPass : public Pass { if (format != "ps") { int modcount = 0; for (auto &mod_it : design->modules) { - if (mod_it.second->attributes.count("\\placeholder") > 0) + if (mod_it.second->get_bool_attribute("\\placeholder") > 0) continue; if (mod_it.second->cells.empty() && mod_it.second->connections.empty()) continue; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index e10ea4cf..7d712d5e 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -113,7 +113,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell RTLIL::Module *mod = new RTLIL::Module; mod->name = celltype; - mod->attributes["\\placeholder"] = RTLIL::Const(0, 0); + mod->attributes["\\placeholder"] = RTLIL::Const(1); design->modules[mod->name] = mod; for (auto &decl : ports) { @@ -147,7 +147,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla } if (cell->parameters.size() == 0) continue; - if (design->modules.at(cell->type)->attributes.count("\\placeholder") > 0) + if (design->modules.at(cell->type)->get_bool_attribute("\\placeholder")) continue; RTLIL::Module *mod = design->modules[cell->type]; cell->type = mod->derive(design, cell->parameters); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 21ef320e..3d75b640 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -47,7 +47,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) wire2driver.insert(sig, cell); } } - if (cell->type == "$memwr" || cell->attributes.count("\\keep")) + if (cell->type == "$memwr" || cell->get_bool_attribute("\\keep")) queue.insert(cell); unused.insert(cell); } diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 75ca4727..c7121959 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -210,7 +210,7 @@ static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs { // detect groups of parallel cases std::vector<int> pgroups(sw->cases.size()); - if (sw->attributes.count("\\parallel_case") == 0) { + if (!sw->get_bool_attribute("\\parallel_case")) { BitPatternPool pool(sw->signal.width); bool extra_group_for_next_case = false; for (size_t i = 0; i < sw->cases.size(); i++) { diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 03d0d181..134211e5 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -144,7 +144,7 @@ struct IopadmapPass : public Pass { cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); if (!nameparam.empty()) cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name)); - cell->attributes["\\keep"] = RTLIL::Const(); + cell->attributes["\\keep"] = RTLIL::Const(1); module->add(cell); wire->port_id = 0; |