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authorClifford Wolf <clifford@clifford.at>2014-09-21 12:57:33 +0200
committerClifford Wolf <clifford@clifford.at>2014-09-21 12:57:33 +0200
commitedf11c635a40c2cfb291089be509b2f31737958b (patch)
tree6b1e7df4ec18e6856743841e233b466dff110414 /passes
parenta7758ef953eccff9295ec9f152ec1b6bef831f89 (diff)
Assert on new logic loops in "share" pass
Diffstat (limited to 'passes')
-rw-r--r--passes/opt/share.cc48
1 files changed, 48 insertions, 0 deletions
diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index c372ed78..02e84584 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -21,6 +21,7 @@
#include "kernel/satgen.h"
#include "kernel/sigtools.h"
#include "kernel/modtools.h"
+#include "kernel/utils.h"
PRIVATE_NAMESPACE_BEGIN
@@ -640,6 +641,48 @@ struct ShareWorker
}
+ // ------------------------------------------------------------------------------------------------
+ // Find SCCs (logic loops). This is only used to make sure that this pass does not introduce loops.
+ // ------------------------------------------------------------------------------------------------
+
+ bool module_has_scc()
+ {
+ SigMap sigmap(module);
+
+ CellTypes ct;
+ ct.setup_internals();
+ ct.setup_stdcells();
+
+ TopoSort<RTLIL::Cell*> toposort;
+ toposort.analyze_loops = false;
+
+ std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bits;
+ std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cells;
+
+ for (auto cell : module->cells())
+ if (ct.cell_known(cell->type))
+ for (auto &conn : cell->connections()) {
+ if (ct.cell_output(cell->type, conn.first))
+ for (auto bit : sigmap(conn.second))
+ cell_to_bits[cell].insert(bit);
+ else
+ for (auto bit : sigmap(conn.second))
+ bit_to_cells[bit].insert(cell);
+ }
+
+ for (auto &it : cell_to_bits)
+ {
+ RTLIL::Cell *c1 = it.first;
+
+ for (auto bit : it.second)
+ for (auto c2 : bit_to_cells[bit])
+ toposort.edge(c1, c2);
+ }
+
+ return !toposort.sort();
+ }
+
+
// -------------
// Setup and run
// -------------
@@ -647,6 +690,8 @@ struct ShareWorker
ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) :
config(config), design(design), module(module)
{
+ bool before_scc = module_has_scc();
+
generic_ops.insert(config.generic_uni_ops.begin(), config.generic_uni_ops.end());
generic_ops.insert(config.generic_bin_ops.begin(), config.generic_bin_ops.end());
generic_ops.insert(config.generic_cbin_ops.begin(), config.generic_cbin_ops.end());
@@ -879,6 +924,9 @@ struct ShareWorker
}
log_assert(recursion_state.empty());
+
+ bool after_scc = before_scc || module_has_scc();
+ log_assert(before_scc == after_scc);
}
};