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authorClifford Wolf <clifford@clifford.at>2015-04-29 07:28:15 +0200
committerClifford Wolf <clifford@clifford.at>2015-04-29 07:28:15 +0200
commitf483dce7c231f83937b5944ed0166a70594a0e8b (patch)
treef9a2dc487da84ba9fcd53d8c56991b1dbe2dd7de /passes
parent9d067fecea8d17dc3e800d09973f5ddaae41774b (diff)
Added $eq/$neq -> $logic_not/$reduce_bool optimization
Diffstat (limited to 'passes')
-rw-r--r--passes/fsm/fsm_extract.cc4
-rw-r--r--passes/opt/opt_const.cc19
2 files changed, 22 insertions, 1 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index 68667ef0..b5250970 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -305,7 +305,9 @@ static void extract_fsm(RTLIL::Wire *wire)
for (auto &cellport : cellport_list) {
RTLIL::Cell *cell = module->cells_.at(cellport.first);
RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
- RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
+ RTLIL::SigSpec sig_b;
+ if (cell->hasPort("\\B"))
+ sig_b = assign_map(cell->getPort("\\B"));
RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y"));
if (cellport.second == "\\A" && !sig_b.is_fully_const())
continue;
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 1758a34f..859d7c64 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -548,6 +548,25 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
}
+ if ((cell->type == "$eq" || cell->type == "$ne") &&
+ (assign_map(cell->getPort("\\A")).is_fully_zero() || assign_map(cell->getPort("\\B")).is_fully_zero()))
+ {
+ cover_list("opt.opt_const.eqneq.cmpzero", "$eq", "$ne", cell->type.str());
+ log("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell),
+ log_id(module), "$eq" ? "$logic_not" : "$reduce_bool");
+ cell->type = cell->type == "$eq" ? "$logic_not" : "$reduce_bool";
+ if (assign_map(cell->getPort("\\A")).is_fully_zero()) {
+ cell->setPort("\\A", cell->getPort("\\B"));
+ cell->setParam("\\A_SIGNED", cell->getParam("\\B_SIGNED"));
+ cell->setParam("\\A_WIDTH", cell->getParam("\\B_WIDTH"));
+ }
+ cell->unsetPort("\\B");
+ cell->unsetParam("\\B_SIGNED");
+ cell->unsetParam("\\B_WIDTH");
+ did_something = true;
+ goto next_cell;
+ }
+
if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx") && assign_map(cell->getPort("\\B")).is_fully_const())
{
bool sign_ext = cell->type == "$sshr" && cell->getParam("\\A_SIGNED").as_bool();