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authorClifford Wolf <clifford@clifford.at>2014-09-06 19:44:11 +0200
committerClifford Wolf <clifford@clifford.at>2014-09-06 19:44:11 +0200
commitfa64942018a39085301d7f24832ad0ad7b0d22f1 (patch)
tree35c826c4ac0b283c3e9f5cd8ef8448afd7425e69 /passes
parent680eaaac41bc64000faa483955279155b0fc0a6b (diff)
Added $macc SAT model
Diffstat (limited to 'passes')
-rw-r--r--passes/tests/test_cell.cc11
1 files changed, 6 insertions, 5 deletions
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 96f08de4..edab51eb 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -42,9 +42,9 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
if (cell_type == "$macc")
{
Macc macc;
- int width = 1 + xorshift32(16);
+ int width = 1 + xorshift32(8);
int depth = 1 + xorshift32(6);
- int mulbits = 0;
+ int mulbits_a = 0, mulbits_b = 0;
RTLIL::Wire *wire_a = module->addWire("\\A");
wire_a->width = 0;
@@ -55,10 +55,11 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
int size_a = xorshift32(width) + 1;
int size_b = xorshift32(width) + 1;
- if (mulbits + size_a*size_b > 256 || xorshift32(2) == 1)
+ if (mulbits_a + size_a*size_b <= 96 && mulbits_b + size_a + size_b <= 16 && xorshift32(2) == 1) {
+ mulbits_a += size_a * size_b;
+ mulbits_b += size_a + size_b;
+ } else
size_b = 0;
- else
- mulbits += size_a*size_b;
Macc::port_t this_port;