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author | Ruben Undheim <ruben.undheim@gmail.com> | 2019-03-28 23:35:03 +0100 |
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committer | Ruben Undheim <ruben.undheim@gmail.com> | 2019-03-28 23:35:03 +0100 |
commit | ff5734b20220e6fb4a3913cf5279ed94bb5156ea (patch) | |
tree | 4c438282926d7bac304ad3ad6ad89523c4c1d784 /techlibs/anlogic/drams.txt | |
parent | db3c67fd6e140893450a44870ee9a75dd1f48b27 (diff) |
Imported GIT HEAD: 0.8+20190328git32bd0f2
Diffstat (limited to 'techlibs/anlogic/drams.txt')
-rw-r--r-- | techlibs/anlogic/drams.txt | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/techlibs/anlogic/drams.txt b/techlibs/anlogic/drams.txt new file mode 100644 index 00000000..4e903c0a --- /dev/null +++ b/techlibs/anlogic/drams.txt @@ -0,0 +1,16 @@ +bram $__ANLOGIC_DRAM16X4 + init 1 + abits 4 + dbits 4 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 1 +endbram + +match $__ANLOGIC_DRAM16X4 + make_outreg +endmatch |