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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2019-03-28 23:36:07 +0100 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2019-03-28 23:36:07 +0100 |
| commit | ba2a8c73889c487be2400372260e18e8a82877f6 (patch) | |
| tree | ec26eec3e633e1d68636a63d9588384631ec2ee5 /techlibs/anlogic/drams_map.v | |
| parent | b08bbcdcfe7c703ad549866f2a22a0c5ecda3dfe (diff) | |
| parent | ff5734b20220e6fb4a3913cf5279ed94bb5156ea (diff) | |
Merge tag 'upstream/0.8+20190328git32bd0f2'
Diffstat (limited to 'techlibs/anlogic/drams_map.v')
| -rw-r--r-- | techlibs/anlogic/drams_map.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/techlibs/anlogic/drams_map.v b/techlibs/anlogic/drams_map.v new file mode 100644 index 00000000..084e2a25 --- /dev/null +++ b/techlibs/anlogic/drams_map.v @@ -0,0 +1,22 @@ +module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [63:0]INIT = 64'bx; + input CLK1; + + input [3:0] A1ADDR; + output [3:0] A1DATA; + + input [3:0] B1ADDR; + input [3:0] B1DATA; + input B1EN; + + EG_LOGIC_DRAM16X4 #( + `include "dram_init_16x4.vh" + ) _TECHMAP_REPLACE_ ( + .di(B1DATA), + .waddr(B1ADDR), + .wclk(CLK1), + .we(B1EN), + .raddr(A1ADDR), + .do(A1DATA) + ); +endmodule |