diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-09-14 13:29:11 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-09-14 13:29:11 +0200 |
| commit | 2c9bd23801fc00463cd218319c7f2f3a89852260 (patch) | |
| tree | a2b0ff142d2c22fda1873b946298825db1c2b389 /techlibs/cmos/testbench.sp | |
| parent | bbe5aa446b413c6298a4b0b13f6fabcd6c984cb6 (diff) | |
Added spice testbench to techlibs/cmos
Diffstat (limited to 'techlibs/cmos/testbench.sp')
| -rw-r--r-- | techlibs/cmos/testbench.sp | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/techlibs/cmos/testbench.sp b/techlibs/cmos/testbench.sp new file mode 100644 index 00000000..95d2f67c --- /dev/null +++ b/techlibs/cmos/testbench.sp @@ -0,0 +1,29 @@ + +* supply voltages +.global Vss Vdd +Vss Vss 0 DC 0 +Vdd Vdd 0 DC 3 + +* simple transistor model +.MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7 +.MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8 + +* load design and library +.include synth.sp +.include cmos_cells.sp + +* input signals +Vclk clk 0 PULSE(0 3 1 0.1 0.1 0.8 2) +Vrst rst 0 PULSE(0 3 0.5 0.1 0.1 2.9 40) +Ven en 0 PULSE(0 3 0.5 0.1 0.1 5.9 8) + +Xuut clk rst en out0 out1 out2 COUNTER + +.tran 0.01 50 + +.control +run +plot v(clk) v(rst)+5 v(en)+10 v(out0)+20 v(out1)+25 v(out2)+30 +.endc + +.end |