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author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-08-30 20:46:20 +0200 |
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committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-08-30 20:46:20 +0200 |
commit | 5033b51947a6ef02cb785b5622e993335efa750a (patch) | |
tree | 7bed18c526bd94917fa2f08e3df12209863698a1 /techlibs/common/simcells.v | |
parent | fefe0fc0430f4f173a25e674708aa0f4f0854b31 (diff) |
New upstream version 0.7+20180830git0b7a184
Diffstat (limited to 'techlibs/common/simcells.v')
-rw-r--r-- | techlibs/common/simcells.v | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index e770c545..937512e7 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -175,6 +175,44 @@ endmodule // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- +//- $_ANDNOT_ (A, B, Y) +//- +//- A 2-input AND-NOT gate. +//- +//- Truth table: A B | Y +//- -----+--- +//- 0 0 | 0 +//- 0 1 | 0 +//- 1 0 | 1 +//- 1 1 | 0 +//- +module \$_ANDNOT_ (A, B, Y); +input A, B; +output Y; +assign Y = A & (~B); +endmodule + +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $_ORNOT_ (A, B, Y) +//- +//- A 2-input OR-NOT gate. +//- +//- Truth table: A B | Y +//- -----+--- +//- 0 0 | 1 +//- 0 1 | 0 +//- 1 0 | 1 +//- 1 1 | 1 +//- +module \$_ORNOT_ (A, B, Y); +input A, B; +output Y; +assign Y = A | (~B); +endmodule + +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- //- $_MUX_ (A, B, S, Y) //- //- A 2-input MUX gate. |