Imported yosys 0.7

1 files changed, 17 insertions, 0 deletions

diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index c4f170a3..e770c545 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -495,6 +495,23 @@ always @(posedge S, posedge R) begin
 end
 endmodule
 
+`ifdef SIMCELLS_FF
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_FF_ (D, Q)
+//-
+//- A D-type flip-flop that is clocked from the implicit global clock. (This cell
+//- type is usually only used in netlists for formal verification.)
+//-
+module \$_FF_ (D, Q);
+input D;
+output reg Q;
+always @($global_clock) begin
+	Q <= D;
+end
+endmodule
+`endif
+
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
 //-     $_DFF_N_ (D, C, Q)