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author | Ruben Undheim <ruben.undheim@gmail.com> | 2016-11-03 23:18:45 +0100 |
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committer | Ruben Undheim <ruben.undheim@gmail.com> | 2016-11-03 23:18:45 +0100 |
commit | 1075138fe86c405f85a6ea3d7c34cf9d6a1c7b0f (patch) | |
tree | 11f9092ecfee4c0d80b589d480e1579c5a40eb8b /techlibs/common/simlib.v | |
parent | 2fba240fc8ec65b60c6cba2ffa022ca532a6817e (diff) | |
parent | fefe0fc0430f4f173a25e674708aa0f4f0854b31 (diff) |
Merge tag 'upstream/0.7'
Diffstat (limited to 'techlibs/common/simlib.v')
-rw-r--r-- | techlibs/common/simlib.v | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 922a47ca..2c4db1ac 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1334,6 +1334,18 @@ endmodule // -------------------------------------------------------- +module \$anyseq (Y); + +parameter WIDTH = 0; + +output [WIDTH-1:0] Y; + +assign Y = 'bx; + +endmodule + +// -------------------------------------------------------- + module \$equiv (A, B, Y); input A, B; @@ -1382,6 +1394,23 @@ endmodule `endif // -------------------------------------------------------- +`ifdef SIMLIB_FF + +module \$ff (D, Q); + +parameter WIDTH = 0; + +input [WIDTH-1:0] D; +output reg [WIDTH-1:0] Q; + +always @($global_clk) begin + Q <= D; +end + +endmodule + +`endif +// -------------------------------------------------------- module \$dff (CLK, D, Q); |