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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-29 19:23:31 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-29 19:23:31 +0200 |
| commit | 2145e57ef08784484e875e64cb43b6d1f4dbe50c (patch) | |
| tree | c9d3fa86b7ec1eaf1b3670522d8eed3f657e7ce9 /techlibs/common/simlib.v | |
| parent | 77e2d39cd079ba98340f55f57e8a6462fb709442 (diff) | |
Bugfix in simlib.v for iverilog
Diffstat (limited to 'techlibs/common/simlib.v')
| -rw-r--r-- | techlibs/common/simlib.v | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 76aa4a52..c2f6cb27 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -455,11 +455,12 @@ input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; generate - if (B_SIGNED) begin:BLOCK1 - assign Y = A[$signed(B) +: Y_WIDTH]; - end else begin:BLOCK2 - assign Y = A[B +: Y_WIDTH]; - end + if (Y_WIDTH > 0) + if (B_SIGNED) begin:BLOCK1 + assign Y = A[$signed(B) +: Y_WIDTH]; + end else begin:BLOCK2 + assign Y = A[B +: Y_WIDTH]; + end endgenerate endmodule |