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author | Clifford Wolf <clifford@clifford.at> | 2014-09-04 02:07:52 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-09-04 02:07:52 +0200 |
commit | 8927aa6148f5575b2da9bfb76afb4af076fe18f3 (patch) | |
tree | 4da0980333589d4785880e48383c6f44e4a94887 /techlibs/common/simlib.v | |
parent | b9cb483f3e2a498ee75a422e09164a920918362b (diff) |
Removed $bu0 cell type
Diffstat (limited to 'techlibs/common/simlib.v')
-rw-r--r-- | techlibs/common/simlib.v | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 61215f59..17700a61 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -55,30 +55,6 @@ endmodule // -------------------------------------------------------- -module \$bu0 (A, Y); - -parameter A_SIGNED = 0; -parameter A_WIDTH = 0; -parameter Y_WIDTH = 0; - -input [A_WIDTH-1:0] A; -output [Y_WIDTH-1:0] Y; - -generate - if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:BLOCK1 - assign Y[A_WIDTH-1:0] = A; - assign Y[Y_WIDTH-1:A_WIDTH] = 0; - end else if (A_SIGNED) begin:BLOCK2 - assign Y = $signed(A); - end else begin:BLOCK3 - assign Y = A; - end -endgenerate - -endmodule - -// -------------------------------------------------------- - module \$pos (A, Y); parameter A_SIGNED = 0; |