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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-30 20:18:48 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-30 20:18:48 +0200 |
| commit | 7daad40ca408732786d46fee8b5485bf45595807 (patch) | |
| tree | 5458b6f3b56f50cca341b6f8962a73999f3e49bd /techlibs/common/stdcells.v | |
| parent | 6400ae36489a7ada5419d7bc502934f6d05e69bb (diff) | |
Fixed counting verilog line numbers for "// synopsys translate_off" sections
Diffstat (limited to 'techlibs/common/stdcells.v')
0 files changed, 0 insertions, 0 deletions