Renamed $_INV_ cell type to $_NOT_

1 files changed, 1 insertions, 1 deletions

diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index 7a4f6b27..190002c0 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -20,7 +20,7 @@
  *  The internal logic cell technology mapper.
  *
  *  This verilog library contains the mapping of internal cells (e.g. $not with
- *  variable bit width) to the internal logic cells (such as the single bit $_INV_ 
+ *  variable bit width) to the internal logic cells (such as the single bit $_NOT_ 
  *  gate). Usually this logic network is then mapped to the actual technology
  *  using e.g. the "abc" pass.
  *