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authorClifford Wolf <clifford@clifford.at>2014-01-18 15:35:15 +0100
committerClifford Wolf <clifford@clifford.at>2014-01-18 15:35:15 +0100
commit5b96675696bb3001232b16a047cb2a9bbf8e3121 (patch)
treec5dc5227dc627655c6c529406bd03e12ba247f7c /techlibs/common
parent839af272adeb6e15c0b1fd1c35249db4a9da9f4d (diff)
Added $bu0 cell to simlib.v
Diffstat (limited to 'techlibs/common')
-rw-r--r--techlibs/common/simlib.v22
1 files changed, 22 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 034244ca..f3d652f0 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -55,6 +55,28 @@ endmodule
// --------------------------------------------------------
+module \$bu0 (A, Y);
+
+parameter A_SIGNED = 0;
+parameter A_WIDTH = 0;
+parameter Y_WIDTH = 0;
+
+`INPUT_A
+output [Y_WIDTH-1:0] Y;
+
+generate
+ if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:A
+ assign Y[A_WIDTH-1:0] = A_BUF.val;
+ assign Y[Y_WIDTH-1:A_WIDTH] = 0;
+ end else begin:B
+ assign Y = +A_BUF.val;
+ end
+endgenerate
+
+endmodule
+
+// --------------------------------------------------------
+
module \$pos (A, Y);
parameter A_SIGNED = 0;