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authorClifford Wolf <clifford@clifford.at>2014-12-08 10:50:19 +0100
committerClifford Wolf <clifford@clifford.at>2014-12-08 10:50:19 +0100
commitf1764b4fe99807c445526774563a98224b642766 (patch)
tree8acab5d97a8f973b75b258036923b209446a9139 /techlibs/common
parentfad9cec47b3aa9fc3d413abee92cc8380d0c0dc4 (diff)
Added $dffe cell type
Diffstat (limited to 'techlibs/common')
-rw-r--r--techlibs/common/simlib.v19
-rw-r--r--techlibs/common/techmap.v2
2 files changed, 20 insertions, 1 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 2d8088ad..e241cd3c 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1217,6 +1217,25 @@ end
endmodule
// --------------------------------------------------------
+
+module \$dffe (CLK, EN, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter EN_POLARITY = 1'b1;
+
+input CLK, EN;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+wire pos_clk = CLK == CLK_POLARITY;
+
+always @(posedge pos_clk) begin
+ if (EN == EN_POLARITY) Q <= D;
+end
+
+endmodule
+
+// --------------------------------------------------------
`ifndef SIMLIB_NOSR
module \$dffsr (CLK, SET, CLR, D, Q);
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index b6c075b6..cb39fb4b 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -59,7 +59,7 @@ module _90_simplemap_various;
endmodule
(* techmap_simplemap *)
-(* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
+(* techmap_celltype = "$sr $dff $dffe $adff $dffsr $dlatch" *)
module _90_simplemap_registers;
endmodule