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authorClifford Wolf <clifford@clifford.at>2014-02-07 17:44:57 +0100
committerClifford Wolf <clifford@clifford.at>2014-02-07 17:44:57 +0100
commitfc3b3c4ec3955b165166d9f44965fac0e1879505 (patch)
tree2552ece4d6e1709f7ef17d838b00f7f774faf95b /techlibs/common
parenta1ac710ab8740ae781e0274f63633e8ed2650da4 (diff)
Added $slice and $concat cell types
Diffstat (limited to 'techlibs/common')
-rw-r--r--techlibs/common/simlib.v30
-rw-r--r--techlibs/common/stdcells.v12
2 files changed, 42 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 87e83bd1..4436abfe 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -829,6 +829,36 @@ endmodule
// --------------------------------------------------------
+module \$slice (A, Y);
+
+parameter OFFSET = 0;
+parameter A_WIDTH = 0;
+parameter Y_WIDTH = 0;
+
+input [A_WIDTH-1:0] A;
+output [Y_WIDTH-1:0] Y;
+
+assign Y = A >> OFFSET;
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$concat (A, B, Y);
+
+parameter A_WIDTH = 0;
+parameter B_WIDTH = 0;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [A_WIDTH+B_WIDTH-1:0] Y;
+
+assign Y = {B, A};
+
+endmodule
+
+// --------------------------------------------------------
+
module \$mux (A, B, S, Y);
parameter WIDTH = 0;
diff --git a/techlibs/common/stdcells.v b/techlibs/common/stdcells.v
index e33e651c..fdee26b6 100644
--- a/techlibs/common/stdcells.v
+++ b/techlibs/common/stdcells.v
@@ -957,6 +957,18 @@ endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
+module \$slice ;
+endmodule
+
+// --------------------------------------------------------
+
+(* techmap_simplemap *)
+module \$concat ;
+endmodule
+
+// --------------------------------------------------------
+
+(* techmap_simplemap *)
module \$mux ;
endmodule