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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-08-30 20:46:22 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-08-30 20:46:22 +0200 |
| commit | 78bfe0de96fa5c6a7e53689ef53deaeac1d0a7b8 (patch) | |
| tree | cc36d8cc573f1e6cc9b15ccc85a66883356cbf5f /techlibs/ecp5/drams_map.v | |
| parent | 291bd6d9b3f51ea86c38bbe998c0896ad8b9fed2 (diff) | |
| parent | 5033b51947a6ef02cb785b5622e993335efa750a (diff) | |
Merge tag 'upstream/0.7+20180830git0b7a184'
Upstream version 0.7+20180830git0b7a184
Diffstat (limited to 'techlibs/ecp5/drams_map.v')
| -rw-r--r-- | techlibs/ecp5/drams_map.v | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/techlibs/ecp5/drams_map.v b/techlibs/ecp5/drams_map.v new file mode 100644 index 00000000..3b3de831 --- /dev/null +++ b/techlibs/ecp5/drams_map.v @@ -0,0 +1,28 @@ +module \$__TRELLIS_DPR16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [63:0] INIT = 64'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [3:0] A1ADDR; + output [3:0] A1DATA; + + input [3:0] B1ADDR; + input [3:0] B1DATA; + input B1EN; + + localparam WCKMUX = CLKPOL2 ? "WCK" : "INV"; + + TRELLIS_DPR16X4 #( + .INITVAL(INIT), + .WCKMUX(WCKMUX), + .WREMUX("WRE") + ) _TECHMAP_REPLACE_ ( + .RAD(A1ADDR), + .DO(A1DATA), + + .WAD(B1ADDR), + .DI(B1DATA), + .WCK(CLK1), + .WRE(B1EN) + ); +endmodule |