New upstream version 0.7+20180830git0b7a184

2 files changed, 33 insertions, 25 deletions

diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index 3a09c157..94794262 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -1,51 +1,59 @@
 module LUT1(output F, input I0);
-  parameter [1:0] INIT = 0;
-  assign F = I0 ? INIT[1] : INIT[0];
+	parameter [1:0] INIT = 0;
+	assign F = I0 ? INIT[1] : INIT[0];
 endmodule
 
 module LUT2(output F, input I0, I1);
-  parameter [3:0] INIT = 0;
-  wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
-  assign F = I0 ? s1[1] : s1[0];
+	parameter [3:0] INIT = 0;
+	wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
+	assign F = I0 ? s1[1] : s1[0];
 endmodule
 
 module LUT3(output F, input I0, I1, I2);
-  parameter [7:0] INIT = 0;
-  wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
-  wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
-  assign F = I0 ? s1[1] : s1[0];
+	parameter [7:0] INIT = 0;
+	wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
+	wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
+	assign F = I0 ? s1[1] : s1[0];
 endmodule
 
 module LUT4(output F, input I0, I1, I2, I3);
-  parameter [15:0] INIT = 0;
-  wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
-  wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
-  wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
-  assign F = I0 ? s1[1] : s1[0];
+	parameter [15:0] INIT = 0;
+	wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
+	wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
+	wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
+	assign F = I0 ? s1[1] : s1[0];
 endmodule
 
 module DFF (output reg Q, input CLK, D);
-	always @(posedge C)
+	parameter [0:0] INIT = 1'b0;
+	initial Q = INIT;
+	always @(posedge CLK)
 		Q <= D;
 endmodule
 
 module DFFN (output reg Q, input CLK, D);
-	always @(negedge C)
+	parameter [0:0] INIT = 1'b0;
+	initial Q = INIT;
+	always @(negedge CLK)
 		Q <= D;
 endmodule
 
 module VCC(output V);
-  assign V = 1;
+	assign V = 1;
 endmodule
 
 module GND(output G);
-  assign G = 0;
+	assign G = 0;
 endmodule
 
 module IBUF(output O, input I);
-  assign O = I;
+	assign O = I;
 endmodule
 
 module OBUF(output O, input I);
-  assign O = I;
+	assign O = I;
+endmodule
+
+module GSR (input GSRI);
+	wire GSRO = GSRI;
 endmodule
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 129ab839..793f345b 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -29,7 +29,7 @@ struct SynthGowinPass : public ScriptPass
 {
 	SynthGowinPass() : ScriptPass("synth_gowin", "synthesis for Gowin FPGAs") { }
 
-	virtual void help() YS_OVERRIDE
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -61,14 +61,14 @@ struct SynthGowinPass : public ScriptPass
 	string top_opt, vout_file;
 	bool retime;
 
-	virtual void clear_flags() YS_OVERRIDE
+	void clear_flags() YS_OVERRIDE
 	{
 		top_opt = "-auto-top";
 		vout_file = "";
 		retime = false;
 	}
 
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		string run_from, run_to;
 		clear_flags();
@@ -111,7 +111,7 @@ struct SynthGowinPass : public ScriptPass
 		log_pop();
 	}
 
-	virtual void script() YS_OVERRIDE
+	void script() YS_OVERRIDE
 	{
 		if (check_label("begin"))
 		{
@@ -169,7 +169,7 @@ struct SynthGowinPass : public ScriptPass
 		if (check_label("vout"))
 		{
 			if (!vout_file.empty() || help_mode)
-				run(stringf("write_verilog -attr2comment -defparam -renameprefix gen %s",
+				run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix gen %s",
 						help_mode ? "<file-name>" : vout_file.c_str()));
 		}
 	}