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author | Clifford Wolf <clifford@clifford.at> | 2015-09-16 09:28:37 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-09-16 09:28:37 +0200 |
commit | c5352f45c3604b60e0bec7a9219d2c139d276573 (patch) | |
tree | 8a0203d00c54c36cbc13d2e74a72abd480a86ec5 /techlibs/greenpak4/cells_sim.v | |
parent | e7c018e5d14c3c609669ab514a7e9111ff006022 (diff) |
Added GreenPAK4 skeleton
Diffstat (limited to 'techlibs/greenpak4/cells_sim.v')
-rw-r--r-- | techlibs/greenpak4/cells_sim.v | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v new file mode 100644 index 00000000..6bcbda8e --- /dev/null +++ b/techlibs/greenpak4/cells_sim.v @@ -0,0 +1,25 @@ +module DFF(input D, CLK, nRSTZ, nSETZ, output reg Q); + always @(posedge CLK, negedge nRSTZ, negedge nSETZ) begin + if (!nRSTZ) + Q <= 1'b0; + else if (!nSETZ) + Q <= 1'b1; + else + Q <= D; + end +endmodule + +module LUT2(input IN0, IN1, output OUT); + parameter [3:0] INIT = 0; + assign OUT = INIT[{IN1, IN0}]; +endmodule + +module LUT3(input IN0, IN1, IN2, output OUT); + parameter [7:0] INIT = 0; + assign OUT = INIT[{IN2, IN1, IN0}]; +endmodule + +module LUT4(input IN0, IN1, IN2, IN3, output OUT); + parameter [15:0] INIT = 0; + assign OUT = INIT[{IN3, IN2, IN1, IN0}]; +endmodule |