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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2016-11-03 23:18:00 +0100 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2016-11-03 23:18:00 +0100 |
| commit | fefe0fc0430f4f173a25e674708aa0f4f0854b31 (patch) | |
| tree | adb13b830212c269d58031f900d652f29013d2d7 /techlibs/ice40/synth_ice40.cc | |
| parent | 4f096fe65b77435daba019248273e547fa18d167 (diff) | |
Imported yosys 0.7
Diffstat (limited to 'techlibs/ice40/synth_ice40.cc')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 38a9cf9d..2533d3af 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -35,7 +35,7 @@ struct SynthIce40Pass : public ScriptPass log("\n"); log(" synth_ice40 [options]\n"); log("\n"); - log("This command runs synthesis for iCE40 FPGAs. This work is experimental.\n"); + log("This command runs synthesis for iCE40 FPGAs.\n"); log("\n"); log(" -top <module>\n"); log(" use the specified module as top module (default='top')\n"); |