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author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-15 23:51:39 +0200 |
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committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-15 23:51:39 +0200 |
commit | 7b99a3646c44759b82d7df0361d59c72776b8aed (patch) | |
tree | bc60a2625efccaaab3fd5e548e0701179be84fd9 /techlibs/ice40 | |
parent | 5033b51947a6ef02cb785b5622e993335efa750a (diff) |
New upstream version 0.7+20181007git9850de4
Diffstat (limited to 'techlibs/ice40')
-rw-r--r-- | techlibs/ice40/cells_sim.v | 39 |
1 files changed, 30 insertions, 9 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 9f73aeb0..e0a07af3 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -920,19 +920,40 @@ parameter A_SIGNED = 1'b0; parameter B_SIGNED = 1'b0; endmodule -(* blackbox *) -module SB_SPRAM256KA( +module SB_SPRAM256KA ( input [13:0] ADDRESS, input [15:0] DATAIN, input [3:0] MASKWREN, - input WREN, - input CHIPSELECT, - input CLOCK, - input STANDBY, - input SLEEP, - input POWEROFF, - output [15:0] DATAOUT + input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF, + output reg [15:0] DATAOUT ); +`ifndef BLACKBOX + reg [15:0] mem [0:16383]; + wire off = SLEEP || !POWEROFF; + integer i; + + always @(negedge POWEROFF) begin + for (i = 0; i <= 16383; i = i+1) + mem[i] = 'bx; + end + + always @(posedge CLOCK, posedge off) begin + if (off) begin + DATAOUT <= 0; + end else + if (CHIPSELECT && !STANDBY && !WREN) begin + DATAOUT <= mem[ADDRESS]; + end else begin + if (CHIPSELECT && !STANDBY && WREN) begin + if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0]; + if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4]; + if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8]; + if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12]; + end + DATAOUT <= 'bx; + end + end +`endif endmodule (* blackbox *) |