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authorClifford Wolf <clifford@clifford.at>2015-04-06 08:44:30 +0200
committerClifford Wolf <clifford@clifford.at>2015-04-06 08:44:30 +0200
commit4389d9306ecb64df29115027ad9a948d852448bd (patch)
tree120ad8f6c7488f7d6c886473f7d66aade9654d23 /techlibs/xilinx/Makefile.inc
parentc0e2b3eb11657fc9a4eb9f04073a4f5f8affaa55 (diff)
Added Xilinx bram black-box modules
Diffstat (limited to 'techlibs/xilinx/Makefile.inc')
-rw-r--r--techlibs/xilinx/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 9af7b58f..18f6764e 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -5,5 +5,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_bb.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))