New upstream version 0.9

1 files changed, 113 insertions, 0 deletions

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index ff5ff072..f4598dcf 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -30,10 +30,15 @@ module GND(output G);
 endmodule
 
 module IBUF(output O, input I);
+  parameter IOSTANDARD = "default";
+  parameter IBUF_LOW_PWR = 0;
   assign O = I;
 endmodule
 
 module OBUF(output O, input I);
+  parameter IOSTANDARD = "default";
+  parameter DRIVE = 12;
+  parameter SLEW = "SLOW";
   assign O = I;
 endmodule
 
@@ -41,6 +46,42 @@ module BUFG(output O, input I);
   assign O = I;
 endmodule
 
+module BUFGCTRL(
+    output O,
+    input I0, input I1,
+    input S0, input S1,
+    input CE0, input CE1,
+    input IGNORE0, input IGNORE1);
+
+parameter [0:0] INIT_OUT = 1'b0;
+parameter PRESELECT_I0 = "FALSE";
+parameter PRESELECT_I1 = "FALSE";
+parameter [0:0] IS_CE0_INVERTED = 1'b0;
+parameter [0:0] IS_CE1_INVERTED = 1'b0;
+parameter [0:0] IS_S0_INVERTED = 1'b0;
+parameter [0:0] IS_S1_INVERTED = 1'b0;
+parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
+parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
+
+wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
+wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
+wire S0_true = (S0 ^ IS_S0_INVERTED);
+wire S1_true = (S1 ^ IS_S1_INVERTED);
+
+assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
+
+endmodule
+
+module BUFHCE(output O, input I, input CE);
+
+parameter [0:0] INIT_OUT = 1'b0;
+parameter CE_TYPE = "SYNC";
+parameter [0:0] IS_CE_INVERTED = 1'b0;
+
+assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
+
+endmodule
+
 // module OBUFT(output O, input I, T);
 //   assign O = T ? 1'bz : I;
 // endmodule
@@ -98,6 +139,22 @@ module LUT6(output O, input I0, I1, I2, I3, I4, I5);
   assign O = I0 ? s1[1] : s1[0];
 endmodule
 
+module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
+  parameter [63:0] INIT = 0;
+  wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
+  wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
+  wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
+  wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
+  wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
+  assign O6 = I0 ? s1[1] : s1[0];
+
+  wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
+  wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
+  wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
+  wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
+  assign O5 = I0 ? s5_1[1] : s5_1[0];
+endmodule
+
 module MUXCY(output O, input CI, DI, S);
   assign O = S ? CI : DI;
 endmodule
@@ -221,6 +278,23 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
+module RAM32X1D (
+  output DPO, SPO,
+  input  D, WCLK, WE,
+  input  A0, A1, A2, A3, A4,
+  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
+);
+  parameter INIT = 32'h0;
+  parameter IS_WCLK_INVERTED = 1'b0;
+  wire [4:0] a = {A4, A3, A2, A1, A0};
+  wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
+  reg [31:0] mem = INIT;
+  assign SPO = mem[a];
+  assign DPO = mem[dpra];
+  wire clk = WCLK ^ IS_WCLK_INVERTED;
+  always @(posedge clk) if (WE) mem[a] <= D;
+endmodule
+
 module RAM64X1D (
   output DPO, SPO,
   input  D, WCLK, WE,
@@ -251,3 +325,42 @@ module RAM128X1D (
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[A] <= D;
 endmodule
+
+module SRL16E (
+  output Q,
+  input A0, A1, A2, A3, CE, CLK, D
+);
+  parameter [15:0] INIT = 16'h0000;
+  parameter [0:0] IS_CLK_INVERTED = 1'b0;
+
+  reg [15:0] r = INIT;
+  assign Q = r[{A3,A2,A1,A0}];
+  generate
+    if (IS_CLK_INVERTED) begin
+      always @(negedge CLK) if (CE) r <= { r[14:0], D };
+    end
+    else
+        always @(posedge CLK) if (CE) r <= { r[14:0], D };
+  endgenerate
+endmodule
+
+module SRLC32E (
+  output Q,
+  output Q31,
+  input [4:0] A,
+  input CE, CLK, D
+);
+  parameter [31:0] INIT = 32'h00000000;
+  parameter [0:0] IS_CLK_INVERTED = 1'b0;
+
+  reg [31:0] r = INIT;
+  assign Q31 = r[31];
+  assign Q = r[A];
+  generate
+    if (IS_CLK_INVERTED) begin
+      always @(negedge CLK) if (CE) r <= { r[30:0], D };
+    end
+    else
+      always @(posedge CLK) if (CE) r <= { r[30:0], D };
+  endgenerate
+endmodule