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authorClifford Wolf <clifford@clifford.at>2015-02-01 17:09:34 +0100
committerClifford Wolf <clifford@clifford.at>2015-02-01 17:09:34 +0100
commit816fe6bbe0ad90f7a696dd208dae6db8139dfd00 (patch)
tree9be22cb0d132ebb6f7c361deb61bb7ebf67f1a8a /techlibs/xilinx/cells_sim.v
parent6978f3a77baa1220ba0f8a41ca26f5f7bc98dd0a (diff)
Added Xilinx example for Basys3 board
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
-rw-r--r--techlibs/xilinx/cells_sim.v6
1 files changed, 5 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 285d63db..c7f07e40 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -19,7 +19,7 @@ module OBUF(output O, input I);
assign O = I;
endmodule
-module BUFGP(output O, input I);
+module BUFG(output O, input I);
assign O = I;
endmodule
@@ -27,6 +27,10 @@ module OBUFT(output O, input I, T);
assign O = T ? 1'bz : I;
endmodule
+module IOBUF(inout IO, output O, input I, T);
+ assign O = IO, IO = T ? 1'bz : I;
+endmodule
+
module INV(output O, input I);
assign O = !I;
endmodule