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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-08-30 20:46:22 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-08-30 20:46:22 +0200 |
| commit | 78bfe0de96fa5c6a7e53689ef53deaeac1d0a7b8 (patch) | |
| tree | cc36d8cc573f1e6cc9b15ccc85a66883356cbf5f /techlibs/xilinx/drams_bb.v | |
| parent | 291bd6d9b3f51ea86c38bbe998c0896ad8b9fed2 (diff) | |
| parent | 5033b51947a6ef02cb785b5622e993335efa750a (diff) | |
Merge tag 'upstream/0.7+20180830git0b7a184'
Upstream version 0.7+20180830git0b7a184
Diffstat (limited to 'techlibs/xilinx/drams_bb.v')
| -rw-r--r-- | techlibs/xilinx/drams_bb.v | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/techlibs/xilinx/drams_bb.v b/techlibs/xilinx/drams_bb.v deleted file mode 100644 index 11168fe1..00000000 --- a/techlibs/xilinx/drams_bb.v +++ /dev/null @@ -1,20 +0,0 @@ - -module RAM64X1D ( - output DPO, SPO, - input D, WCLK, WE, - input A0, A1, A2, A3, A4, A5, - input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 -); - parameter INIT = 64'h0; - parameter IS_WCLK_INVERTED = 1'b0; -endmodule - -module RAM128X1D ( - output DPO, SPO, - input D, WCLK, WE, - input [6:0] A, DPRA -); - parameter INIT = 128'h0; - parameter IS_WCLK_INVERTED = 1'b0; -endmodule - |