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authorClifford Wolf <clifford@clifford.at>2015-04-09 13:37:07 +0200
committerClifford Wolf <clifford@clifford.at>2015-04-09 13:37:07 +0200
commit229825e1b8936bd346829cf0ec9cf1fb3a67fc19 (patch)
tree818b40a9362b445de1dc247486d9d87a34b2b2cf /techlibs/xilinx/drams_bb.v
parent25781e329b51ca84e5fd697705cb0377af64f90b (diff)
Xilinx DRAMS: RAM64X1D, RAM128X1D
Diffstat (limited to 'techlibs/xilinx/drams_bb.v')
-rw-r--r--techlibs/xilinx/drams_bb.v19
1 files changed, 14 insertions, 5 deletions
diff --git a/techlibs/xilinx/drams_bb.v b/techlibs/xilinx/drams_bb.v
index f3169ab4..11168fe1 100644
--- a/techlibs/xilinx/drams_bb.v
+++ b/techlibs/xilinx/drams_bb.v
@@ -1,11 +1,20 @@
-module RAM32X1D (
+module RAM64X1D (
output DPO, SPO,
- input A0, A1, A2, A3, A4, D,
- input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4,
- input WCLK, WE
+ input D, WCLK, WE,
+ input A0, A1, A2, A3, A4, A5,
+ input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
- parameter INIT = 32'h0;
+ parameter INIT = 64'h0;
+ parameter IS_WCLK_INVERTED = 1'b0;
+endmodule
+
+module RAM128X1D (
+ output DPO, SPO,
+ input D, WCLK, WE,
+ input [6:0] A, DPRA
+);
+ parameter INIT = 128'h0;
parameter IS_WCLK_INVERTED = 1'b0;
endmodule