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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-09 08:17:14 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-09 08:17:14 +0200 |
| commit | b00cad81d76bd83fe3210f8b84dec8c34acb7fd9 (patch) | |
| tree | 49aba5ace93677d5423d9a19a8acfc9e65f295ae /techlibs/xilinx/drams_bb.v | |
| parent | 21a1cc1b60f0c646dcc46c89440fc1a2cf606743 (diff) | |
Towards DRAM support in Xilinx flow
Diffstat (limited to 'techlibs/xilinx/drams_bb.v')
| -rw-r--r-- | techlibs/xilinx/drams_bb.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/techlibs/xilinx/drams_bb.v b/techlibs/xilinx/drams_bb.v new file mode 100644 index 00000000..f3169ab4 --- /dev/null +++ b/techlibs/xilinx/drams_bb.v @@ -0,0 +1,11 @@ + +module RAM32X1D ( + output DPO, SPO, + input A0, A1, A2, A3, A4, D, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, + input WCLK, WE +); + parameter INIT = 32'h0; + parameter IS_WCLK_INVERTED = 1'b0; +endmodule + |