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authorRuben Undheim <ruben.undheim@gmail.com>2019-10-18 19:56:51 +0000
committerRuben Undheim <ruben.undheim@gmail.com>2019-10-18 19:56:51 +0000
commit1f6bb85359149a016811e7e7fef980c3d45211e7 (patch)
tree749672f9a104cbfb25bb02acad6cb731724b9d56 /techlibs/xilinx/drams_map.v
parentff5734b20220e6fb4a3913cf5279ed94bb5156ea (diff)
New upstream version 0.9
Diffstat (limited to 'techlibs/xilinx/drams_map.v')
-rw-r--r--techlibs/xilinx/drams_map.v34
1 files changed, 34 insertions, 0 deletions
diff --git a/techlibs/xilinx/drams_map.v b/techlibs/xilinx/drams_map.v
index 47476b59..77041ca8 100644
--- a/techlibs/xilinx/drams_map.v
+++ b/techlibs/xilinx/drams_map.v
@@ -1,4 +1,38 @@
+module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+ parameter [31:0] INIT = 32'bx;
+ parameter CLKPOL2 = 1;
+ input CLK1;
+
+ input [4:0] A1ADDR;
+ output A1DATA;
+
+ input [4:0] B1ADDR;
+ input B1DATA;
+ input B1EN;
+
+ RAM32X1D #(
+ .INIT(INIT),
+ .IS_WCLK_INVERTED(!CLKPOL2)
+ ) _TECHMAP_REPLACE_ (
+ .DPRA0(A1ADDR[0]),
+ .DPRA1(A1ADDR[1]),
+ .DPRA2(A1ADDR[2]),
+ .DPRA3(A1ADDR[3]),
+ .DPRA4(A1ADDR[4]),
+ .DPO(A1DATA),
+
+ .A0(B1ADDR[0]),
+ .A1(B1ADDR[1]),
+ .A2(B1ADDR[2]),
+ .A3(B1ADDR[3]),
+ .A4(B1ADDR[4]),
+ .D(B1DATA),
+ .WCLK(CLK1),
+ .WE(B1EN)
+ );
+endmodule
+
module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
parameter [63:0] INIT = 64'bx;
parameter CLKPOL2 = 1;