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authorClifford Wolf <clifford@clifford.at>2015-04-09 08:17:14 +0200
committerClifford Wolf <clifford@clifford.at>2015-04-09 08:17:14 +0200
commitb00cad81d76bd83fe3210f8b84dec8c34acb7fd9 (patch)
tree49aba5ace93677d5423d9a19a8acfc9e65f295ae /techlibs/xilinx/drams_map.v
parent21a1cc1b60f0c646dcc46c89440fc1a2cf606743 (diff)
Towards DRAM support in Xilinx flow
Diffstat (limited to 'techlibs/xilinx/drams_map.v')
-rw-r--r--techlibs/xilinx/drams_map.v35
1 files changed, 35 insertions, 0 deletions
diff --git a/techlibs/xilinx/drams_map.v b/techlibs/xilinx/drams_map.v
new file mode 100644
index 00000000..c0825150
--- /dev/null
+++ b/techlibs/xilinx/drams_map.v
@@ -0,0 +1,35 @@
+
+module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+ parameter [31:0] INIT = 32'bx;
+ parameter CLKPOL2 = 1;
+ input CLK1;
+
+ input [4:0] A1ADDR;
+ output A1DATA;
+
+ input [4:0] B1ADDR;
+ input B1DATA;
+ input B1EN;
+
+ RAM32X1D #(
+ .INIT(INIT),
+ .IS_WCLK_INVERTED(!CLKPOL2)
+ ) _TECHMAP_REPLACE_ (
+ .DPRA0(A1ADDR[0]),
+ .DPRA1(A1ADDR[1]),
+ .DPRA2(A1ADDR[2]),
+ .DPRA3(A1ADDR[3]),
+ .DPRA4(A1ADDR[4]),
+ .DPO(A1DATA),
+
+ .A0(B1ADDR[0]),
+ .A1(B1ADDR[1]),
+ .A2(B1ADDR[2]),
+ .A3(B1ADDR[3]),
+ .A4(B1ADDR[4]),
+ .D(B1DATA),
+ .WCLK(CLK1),
+ .WE(B1EN)
+ );
+endmodule
+