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authorClifford Wolf <clifford@clifford.at>2015-02-01 17:09:34 +0100
committerClifford Wolf <clifford@clifford.at>2015-02-01 17:09:34 +0100
commit816fe6bbe0ad90f7a696dd208dae6db8139dfd00 (patch)
tree9be22cb0d132ebb6f7c361deb61bb7ebf67f1a8a /techlibs/xilinx/example_basys3/example.v
parent6978f3a77baa1220ba0f8a41ca26f5f7bc98dd0a (diff)
Added Xilinx example for Basys3 board
Diffstat (limited to 'techlibs/xilinx/example_basys3/example.v')
-rw-r--r--techlibs/xilinx/example_basys3/example.v21
1 files changed, 21 insertions, 0 deletions
diff --git a/techlibs/xilinx/example_basys3/example.v b/techlibs/xilinx/example_basys3/example.v
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+++ b/techlibs/xilinx/example_basys3/example.v
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+module example(CLK, LD);
+ input CLK;
+ output [15:0] LD;
+
+ wire clock;
+ reg [15:0] leds;
+
+ BUFG CLK_BUF (.I(CLK), .O(clock));
+ OBUF LD_BUF[15:0] (.I(leds), .O(LD));
+
+ parameter COUNTBITS = 26;
+ reg [COUNTBITS-1:0] counter;
+
+ always @(posedge CLK) begin
+ counter <= counter + 1;
+ if (counter[COUNTBITS-1])
+ leds <= 16'h8000 >> counter[COUNTBITS-2:COUNTBITS-5];
+ else
+ leds <= 16'h0001 << counter[COUNTBITS-2:COUNTBITS-5];
+ end
+endmodule