summaryrefslogtreecommitdiff
path: root/techlibs/xilinx/example_basys3/example.xdc
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2015-10-13 15:40:21 +0200
committerClifford Wolf <clifford@clifford.at>2015-10-13 15:41:20 +0200
commitf42218682d2c7caa6caa81cb2ca48f0c3f62bb5b (patch)
treeeed220c7c84c673dec27bca4c2e96d919831f8b7 /techlibs/xilinx/example_basys3/example.xdc
parentf13e3873212fb4338ee3dd180cb9b0cd3d134935 (diff)
Added examples/ top-level directory
Diffstat (limited to 'techlibs/xilinx/example_basys3/example.xdc')
-rw-r--r--techlibs/xilinx/example_basys3/example.xdc21
1 files changed, 0 insertions, 21 deletions
diff --git a/techlibs/xilinx/example_basys3/example.xdc b/techlibs/xilinx/example_basys3/example.xdc
deleted file mode 100644
index c1fd0e92..00000000
--- a/techlibs/xilinx/example_basys3/example.xdc
+++ /dev/null
@@ -1,21 +0,0 @@
-
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W5 } [get_ports CLK]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U16 } [get_ports {LD[0]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN E19 } [get_ports {LD[1]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U19 } [get_ports {LD[2]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V19 } [get_ports {LD[3]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W18 } [get_ports {LD[4]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U15 } [get_ports {LD[5]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U14 } [get_ports {LD[6]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V14 } [get_ports {LD[7]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V13 } [get_ports {LD[8]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V3 } [get_ports {LD[9]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W3 } [get_ports {LD[10]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U3 } [get_ports {LD[11]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN P3 } [get_ports {LD[12]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN N3 } [get_ports {LD[13]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN P1 } [get_ports {LD[14]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN L1 } [get_ports {LD[15]}]
-
-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
-