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authorClifford Wolf <clifford@clifford.at>2015-10-13 14:21:20 +0200
committerClifford Wolf <clifford@clifford.at>2015-10-13 14:21:20 +0200
commitf13e3873212fb4338ee3dd180cb9b0cd3d134935 (patch)
treef2cfe06b4332859abb143fe4ed69f054de491522 /techlibs/xilinx/example_basys3/run_prog.tcl
parent34f34be17c891ffb99ca76700634aeff9da76bde (diff)
SystemVerilog also has assume(), added implicit -D FORMAL
Diffstat (limited to 'techlibs/xilinx/example_basys3/run_prog.tcl')
0 files changed, 0 insertions, 0 deletions