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authorClifford Wolf <clifford@clifford.at>2015-02-01 17:09:34 +0100
committerClifford Wolf <clifford@clifford.at>2015-02-01 17:09:34 +0100
commit816fe6bbe0ad90f7a696dd208dae6db8139dfd00 (patch)
tree9be22cb0d132ebb6f7c361deb61bb7ebf67f1a8a /techlibs/xilinx/example_basys3/run_yosys.ys
parent6978f3a77baa1220ba0f8a41ca26f5f7bc98dd0a (diff)
Added Xilinx example for Basys3 board
Diffstat (limited to 'techlibs/xilinx/example_basys3/run_yosys.ys')
-rw-r--r--techlibs/xilinx/example_basys3/run_yosys.ys2
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diff --git a/techlibs/xilinx/example_basys3/run_yosys.ys b/techlibs/xilinx/example_basys3/run_yosys.ys
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+read_verilog example.v
+synth_xilinx -edif example.edif -top example