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authorClifford Wolf <clifford@clifford.at>2015-02-01 17:10:46 +0100
committerClifford Wolf <clifford@clifford.at>2015-02-01 17:10:46 +0100
commit3cbfa3815ee0c40fcafe80d56afec97c36368f06 (patch)
tree4f1ccade1714d31d8bb1443b4a1735a3174f0492 /techlibs/xilinx/example_sim_counter/counter_tb.v
parent816fe6bbe0ad90f7a696dd208dae6db8139dfd00 (diff)
Removed old XST-based xilinx examples
Diffstat (limited to 'techlibs/xilinx/example_sim_counter/counter_tb.v')
-rw-r--r--techlibs/xilinx/example_sim_counter/counter_tb.v61
1 files changed, 0 insertions, 61 deletions
diff --git a/techlibs/xilinx/example_sim_counter/counter_tb.v b/techlibs/xilinx/example_sim_counter/counter_tb.v
deleted file mode 100644
index b6b64269..00000000
--- a/techlibs/xilinx/example_sim_counter/counter_tb.v
+++ /dev/null
@@ -1,61 +0,0 @@
-`timescale 1 ns / 1 ps
-
-module testbench;
-
-reg clk, en, rst;
-wire [3:0] count;
-
-counter uut_counter(
- .clk(clk),
- .count(count),
- .en(en),
- .rst(rst)
-);
-
-initial begin
- clk <= 0;
- forever begin
- #50;
- clk <= ~clk;
- end
-end
-
-initial begin
- @(posedge clk);
- forever begin
- @(posedge clk);
- $display("%d", count);
- end
-end
-
-initial begin
- rst <= 1; en <= 0; @(posedge clk);
- rst <= 1; en <= 0; @(posedge clk);
- rst <= 0; en <= 0; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 0; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 1; en <= 1; @(posedge clk);
- rst <= 0; en <= 0; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 0; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 0; @(posedge clk);
- rst <= 1; en <= 0; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 0; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 0; @(posedge clk);
- rst <= 0; en <= 1; @(posedge clk);
- rst <= 0; en <= 0; @(posedge clk);
- $finish;
-end
-
-endmodule