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authorClifford Wolf <clifford@clifford.at>2015-02-01 17:10:46 +0100
committerClifford Wolf <clifford@clifford.at>2015-02-01 17:10:46 +0100
commit3cbfa3815ee0c40fcafe80d56afec97c36368f06 (patch)
tree4f1ccade1714d31d8bb1443b4a1735a3174f0492 /techlibs/xilinx/example_sim_counter/run_sim.sh
parent816fe6bbe0ad90f7a696dd208dae6db8139dfd00 (diff)
Removed old XST-based xilinx examples
Diffstat (limited to 'techlibs/xilinx/example_sim_counter/run_sim.sh')
-rw-r--r--techlibs/xilinx/example_sim_counter/run_sim.sh23
1 files changed, 0 insertions, 23 deletions
diff --git a/techlibs/xilinx/example_sim_counter/run_sim.sh b/techlibs/xilinx/example_sim_counter/run_sim.sh
deleted file mode 100644
index b8354c00..00000000
--- a/techlibs/xilinx/example_sim_counter/run_sim.sh
+++ /dev/null
@@ -1,23 +0,0 @@
-#!/bin/bash
-
-set -ex
-
-XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE
-
-../../../yosys -p 'synth_xilinx -top counter; write_verilog -noattr testbench_synth.v' counter.v
-
-iverilog -o testbench_gold counter_tb.v counter.v
-iverilog -o testbench_gate counter_tb.v testbench_synth.v \
- $XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6,BUFGP,IBUF}}.v
-
-./testbench_gold > testbench_gold.txt
-./testbench_gate > testbench_gate.txt
-
-if diff -u testbench_gold.txt testbench_gate.txt; then
- set +x; echo; echo; banner " PASS "
-else
- exit 1
-fi
-
-rm -f testbench_{synth,gold,gate,mapped}*
-