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authorClifford Wolf <clifford@clifford.at>2013-10-27 09:52:00 +0100
committerClifford Wolf <clifford@clifford.at>2013-10-27 09:58:53 +0100
commit88cd2eadf5f889eb0187f25789a9e6bd95ccdb7b (patch)
treedb06570b693a049a3e0ce696898df936230b3cc1 /techlibs/xilinx/example_sim_counter/run_sim.sh
parent4a3669d871dccf7ff772ad584b9f1271f75e4eb5 (diff)
Cleanups in xilinx examples
Diffstat (limited to 'techlibs/xilinx/example_sim_counter/run_sim.sh')
-rw-r--r--techlibs/xilinx/example_sim_counter/run_sim.sh23
1 files changed, 23 insertions, 0 deletions
diff --git a/techlibs/xilinx/example_sim_counter/run_sim.sh b/techlibs/xilinx/example_sim_counter/run_sim.sh
new file mode 100644
index 00000000..e26d00db
--- /dev/null
+++ b/techlibs/xilinx/example_sim_counter/run_sim.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+
+set -ex
+
+XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE
+
+../../../yosys -p 'synth_xilinx -top counter; write_verilog -noattr testbench_synth.v' counter.v
+
+iverilog -o testbench_gold counter_tb.v counter.v
+iverilog -o testbench_gate counter_tb.v testbench_synth.v \
+ $XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6}}.v
+
+./testbench_gold > testbench_gold.txt
+./testbench_gate > testbench_gate.txt
+
+if diff -u testbench_gold.txt testbench_gate.txt; then
+ set +x; echo; echo; banner " PASS "
+else
+ exit 1
+fi
+
+rm -f testbench_{synth,gold,gate,mapped}*
+