diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-02-01 17:10:46 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-01 17:10:46 +0100 |
| commit | 3cbfa3815ee0c40fcafe80d56afec97c36368f06 (patch) | |
| tree | 4f1ccade1714d31d8bb1443b4a1735a3174f0492 /techlibs/xilinx/example_zed_counter/README | |
| parent | 816fe6bbe0ad90f7a696dd208dae6db8139dfd00 (diff) | |
Removed old XST-based xilinx examples
Diffstat (limited to 'techlibs/xilinx/example_zed_counter/README')
| -rw-r--r-- | techlibs/xilinx/example_zed_counter/README | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/techlibs/xilinx/example_zed_counter/README b/techlibs/xilinx/example_zed_counter/README deleted file mode 100644 index 539f24e7..00000000 --- a/techlibs/xilinx/example_zed_counter/README +++ /dev/null @@ -1,10 +0,0 @@ - -This is a simple example for Yosys synthesis targeting the ZED FPGA -development board [1, 2]. Simple script for xst-based synthesis (incl. -generation of reference edif files) and uploading to the board can be -found here [3]. - -[1] http://www.zedboard.org/ -[2] https://www.xilinx.com/zynq/ -[3] http://verilog.james.walms.co.uk/ - |