summaryrefslogtreecommitdiff
path: root/techlibs/xilinx/example_zed_counter/README
diff options
context:
space:
mode:
authorJames Walmsley <james@fullfat-fs.co.uk>2013-10-27 21:48:39 +0100
committerJames Walmsley <james@fullfat-fs.co.uk>2013-10-27 21:48:39 +0100
commit40b3551b45ea4a9901f68f1ecd0983270973a1f1 (patch)
treed3b3542d06ac5c5067c7cd73a0d75b486e4a50a9 /techlibs/xilinx/example_zed_counter/README
parentf39c0c992839fb79f667d404a6edc85bcb662dcf (diff)
[EXAMPLES] Ported the mojo counter example to Zynq ZED board.
Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days.
Diffstat (limited to 'techlibs/xilinx/example_zed_counter/README')
-rw-r--r--techlibs/xilinx/example_zed_counter/README10
1 files changed, 10 insertions, 0 deletions
diff --git a/techlibs/xilinx/example_zed_counter/README b/techlibs/xilinx/example_zed_counter/README
new file mode 100644
index 00000000..539f24e7
--- /dev/null
+++ b/techlibs/xilinx/example_zed_counter/README
@@ -0,0 +1,10 @@
+
+This is a simple example for Yosys synthesis targeting the ZED FPGA
+development board [1, 2]. Simple script for xst-based synthesis (incl.
+generation of reference edif files) and uploading to the board can be
+found here [3].
+
+[1] http://www.zedboard.org/
+[2] https://www.xilinx.com/zynq/
+[3] http://verilog.james.walms.co.uk/
+