Removed old XST-based xilinx examples

4 files changed, 0 insertions, 56 deletions

diff --git a/techlibs/xilinx/example_zed_counter/README b/techlibs/xilinx/example_zed_counter/README
deleted file mode 100644
index 539f24e7..00000000
--- a/techlibs/xilinx/example_zed_counter/README
+++ /dev/null
@@ -1,10 +0,0 @@
-
-This is a simple example for Yosys synthesis targeting the ZED FPGA
-development board [1, 2]. Simple script for xst-based synthesis (incl.
-generation of reference edif files) and uploading to the board can be
-found here [3].
-
-[1] http://www.zedboard.org/
-[2] https://www.xilinx.com/zynq/
-[3] http://verilog.james.walms.co.uk/
-
diff --git a/techlibs/xilinx/example_zed_counter/example.sh b/techlibs/xilinx/example_zed_counter/example.sh
deleted file mode 100644
index d0fcd832..00000000
--- a/techlibs/xilinx/example_zed_counter/example.sh
+++ /dev/null
@@ -1,18 +0,0 @@
-#!/bin/bash
-
-set -ex
-
-XILINX_DIR=/opt/Xilinx/14.7/ISE_DS/ISE
-XILINX_PART=xc7z020clg484-1
-
-yosys - <<- EOT
-	read_verilog example.v
-	synth_xilinx -edif synth.edif
-EOT
-
-$XILINX_DIR/bin/lin64/edif2ngd -a synth.edif synth.ngo
-$XILINX_DIR/bin/lin64/ngdbuild -p $XILINX_PART -uc example.ucf synth.ngo synth.ngd
-$XILINX_DIR/bin/lin64/map -p $XILINX_PART -w -o mapped.ncd synth.ngd constraints.pcf
-$XILINX_DIR/bin/lin64/par -w mapped.ncd placed.ncd constraints.pcf
-$XILINX_DIR/bin/lin64/bitgen -w placed.ncd example.bit constraints.pcf
-$XILINX_DIR/bin/lin64/promgen -w -b -p bin -o example.bin -u 0 example.bit -data_width 32
diff --git a/techlibs/xilinx/example_zed_counter/example.ucf b/techlibs/xilinx/example_zed_counter/example.ucf
deleted file mode 100644
index dadc8373..00000000
--- a/techlibs/xilinx/example_zed_counter/example.ucf
+++ /dev/null
@@ -1,14 +0,0 @@
-NET "clk" TNM_NET = clk;
-TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;
-
-NET "clk" LOC = Y9		| IOSTANDARD=LVCMOS33;  # "GCLK"
-NET "ctrl" LOC = P16	| IOSTANDARD=LVCMOS18;  # "BTNC"
-
-NET "led_0" LOC = T22 | IOSTANDARD=LVCMOS33;  # "LD0"
-NET "led_1" LOC = T21 | IOSTANDARD=LVCMOS33;  # "LD0"
-NET "led_2" LOC = U22 | IOSTANDARD=LVCMOS33;  # "LD0"
-NET "led_3" LOC = U21 | IOSTANDARD=LVCMOS33;  # "LD0"
-NET "led_4" LOC = V22 | IOSTANDARD=LVCMOS33;  # "LD0"
-NET "led_5" LOC = W22 | IOSTANDARD=LVCMOS33;  # "LD0"
-NET "led_6" LOC = U19 | IOSTANDARD=LVCMOS33;  # "LD0"
-NET "led_7" LOC = U14 | IOSTANDARD=LVCMOS33;  # "LD0"
diff --git a/techlibs/xilinx/example_zed_counter/example.v b/techlibs/xilinx/example_zed_counter/example.v
deleted file mode 100644
index cb98cc1b..00000000
--- a/techlibs/xilinx/example_zed_counter/example.v
+++ /dev/null
@@ -1,14 +0,0 @@
-module top(clk, ctrl, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0);
-
-input clk, ctrl;
-output led_7, led_6, led_5, led_4;
-output led_3, led_2, led_1, led_0;
-
-reg [31:0] counter;
-
-always @(posedge clk)
-	counter <= counter + (ctrl ? 4 : 1);
-
-assign {led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0} = counter >> 24;
-
-endmodule