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authorClifford Wolf <clifford@clifford.at>2013-11-24 19:50:25 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-24 19:50:25 +0100
commit20175afd298be717aa91a96c9d8654859cf2dd2d (patch)
tree4dd05b42f8f76b07dc05c6453b2f7530140b062d /techlibs/xilinx/synth_xilinx.cc
parent019b3015418aaf848313ca05ce1ac59df1715052 (diff)
Added "techmap -share_map" option
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
-rw-r--r--techlibs/xilinx/synth_xilinx.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 78c7a8af..ff906db8 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -82,7 +82,7 @@ struct SynthXilinxPass : public Pass {
log(" clean\n");
log("\n");
log(" map_cells:\n");
- log(" techmap -map <share_dir>/xilinx/cells.v\n");
+ log(" techmap -share_map xilinx/cells.v\n");
log(" clean\n");
log("\n");
log(" clkbuf:\n");
@@ -94,7 +94,7 @@ struct SynthXilinxPass : public Pass {
log(" iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks\n");
log("\n");
log(" edif:\n");
- log(" write_edif -top <top> synth.edif\n");
+ log(" write_edif synth.edif\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
@@ -182,7 +182,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "map_cells"))
{
- Pass::call(design, stringf("techmap -map %s", get_share_file_name("xilinx/cells.v").c_str()));
+ Pass::call(design, "techmap -share_map xilinx/cells.v");
Pass::call(design, "clean");
}
@@ -201,7 +201,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "edif"))
{
if (!edif_file.empty())
- Pass::call(design, stringf("write_edif -top %s %s", top_module.c_str(), edif_file.c_str()));
+ Pass::call(design, stringf("write_edif %s", edif_file.c_str()));
}
log_pop();