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authorClifford Wolf <clifford@clifford.at>2015-04-06 08:44:30 +0200
committerClifford Wolf <clifford@clifford.at>2015-04-06 08:44:30 +0200
commit4389d9306ecb64df29115027ad9a948d852448bd (patch)
tree120ad8f6c7488f7d6c886473f7d66aade9654d23 /techlibs/xilinx/synth_xilinx.cc
parentc0e2b3eb11657fc9a4eb9f04073a4f5f8affaa55 (diff)
Added Xilinx bram black-box modules
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
-rw-r--r--techlibs/xilinx/synth_xilinx.cc2
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 8aebf302..aac8e912 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -69,6 +69,7 @@ struct SynthXilinxPass : public Pass {
log("\n");
log(" begin:\n");
log(" read_verilog -lib +/xilinx/cells_sim.v\n");
+ log(" read_verilog -lib +/xilinx/brams_bb.v\n");
log(" hierarchy -check -top <top>\n");
log("\n");
log(" flatten: (only if -flatten)\n");
@@ -158,6 +159,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "begin"))
{
Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
+ Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
}