Added read-enable to memory model

1 files changed, 2 insertions, 2 deletions

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b3d4c214..ee67beba 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -79,7 +79,6 @@ struct SynthXilinxPass : public Pass {
 		log("\n");
 		log("    coarse:\n");
 		log("        synth -run coarse\n");
-		log("        dff2dffe\n");
 		log("\n");
 		log("    bram:\n");
 		log("        memory_bram -rules +/xilinx/brams.txt\n");
@@ -92,6 +91,7 @@ struct SynthXilinxPass : public Pass {
 		log("    fine:\n");
 		log("        opt -fast -full\n");
 		log("        memory_map\n");
+		log("        dff2dffe\n");
 		log("        opt -full\n");
 		log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
 		log("        opt -fast\n");
@@ -178,7 +178,6 @@ struct SynthXilinxPass : public Pass {
 		if (check_label(active, run_from, run_to, "coarse"))
 		{
 			Pass::call(design, "synth -run coarse");
-			Pass::call(design, "dff2dffe");
 		}
 
 		if (check_label(active, run_from, run_to, "bram"))
@@ -197,6 +196,7 @@ struct SynthXilinxPass : public Pass {
 		{
 			Pass::call(design, "opt -fast -full");
 			Pass::call(design, "memory_map");
+			Pass::call(design, "dff2dffe");
 			Pass::call(design, "opt -full");
 			Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
 			Pass::call(design, "opt -fast");