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authorClifford Wolf <clifford@clifford.at>2015-05-26 17:04:37 +0200
committerClifford Wolf <clifford@clifford.at>2015-05-26 17:08:53 +0200
commitc329233f0de691d818cc8b1aff3dd23cebf38949 (patch)
tree4eb622a5d7b0d355807043d647c7ccff60261b43 /techlibs/xilinx/synth_xilinx.cc
parent08a4af3cde27acb57085d2eac5f897310d98a06e (diff)
Added output args to synth_ice40
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
-rw-r--r--techlibs/xilinx/synth_xilinx.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 0e2fdac7..8ef0fae1 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -110,8 +110,8 @@ struct SynthXilinxPass : public Pass {
log(" stat\n");
log(" check -noinit\n");
log("\n");
- log(" edif:\n");
- log(" write_edif synth.edif\n");
+ log(" edif: (only if -edif)\n");
+ log(" write_edif <file-name>\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)