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authorClifford Wolf <clifford@clifford.at>2015-01-06 23:54:33 +0100
committerClifford Wolf <clifford@clifford.at>2015-01-06 23:54:33 +0100
commit08c13f635cb59f701b51a14caf608c503b6eecb1 (patch)
tree7b2a530284c388da54decd9fb0d495d529799388 /techlibs/xilinx/tests/bram1_tb.v
parentec2eef89fab03beb655f4fe3a16b002d3bf439f7 (diff)
Xilinx RAMB36/RAMB18 memory_bram support complete
Diffstat (limited to 'techlibs/xilinx/tests/bram1_tb.v')
-rw-r--r--techlibs/xilinx/tests/bram1_tb.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/tests/bram1_tb.v b/techlibs/xilinx/tests/bram1_tb.v
index ff0929da..6ed04d4a 100644
--- a/techlibs/xilinx/tests/bram1_tb.v
+++ b/techlibs/xilinx/tests/bram1_tb.v
@@ -21,7 +21,7 @@ module bram1_tb #(
.RD_DATA(RD_DATA)
);
- reg [63:0] xorshift64_state = 64'd88172645463325252;
+ reg [63:0] xorshift64_state = 64'd88172645463325252 ^ (ABITS << 24) ^ (DBITS << 16) ^ (TRANSP << 8);
task xorshift64_next;
begin